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general description the max5360/max5361/max5362 are low-cost, 6-bit digital-to-analog converters (dacs) in miniature 5-pin sot23 packages with a simple 2-wire serial interface that allows communication with multiple devices. the max5360 has an internal +2v reference and operates from a +2.7v to +3.6v supply. the max5361 has an internal +4v reference and operates from a +4.5v to +5.5v supply. the max5362 operates over the full +2.7v to +5.5v supply range and has an internal refer- ence equal to 0.9 v dd . the fast-mode i 2 c-compatible serial interface allows communication at data rates up to 400kbps, minimizing board space and reducing interconnect complexity in many applications. each device is available with one of four factory-preset addresses (see selector guide ). the max5360/max5361/max5362 also include an out- put buffer, a low-power shutdown mode, and a power- on reset that ensures the dac outputs are at zero when power is initially applied. in shutdown mode, the supply current is reduced to less than 1? and the output is pulled down with a 10k resistor to gnd. the max5360/max5361/max5362 are available in miniature 5-pin sot23 packages. applications automatic tuning (vco) power amplifier bias control programmable threshold levels automatic gain control automatic offset adjustment features 6-bit accuracy in a tiny 5-pin sot23 package wide +2.7v to +5.5v supply range (max5362) 1? shutdown mode buffered output drives resistive loads low glitch power-on-reset to zero dac output fast i 2 c-compatible serial interface -5% full-scale error (max5362) 1lsb (max) inl/dnl low 230? max supply current max5360/max5361/max5362 low-cost, low-power 6-bit dacs with 2-wire serial interface in sot23 package ________________________________________________________________ maxim integrated products 1 gnd sda v dd 15 scl out max5360 max5361 max5362 sot23-5 top view 2 34 px.1/scl +2.7v to +5.5v px.0/sda gnd c v dd scl sda out gnd v dd max5362 typical operating circuit 19-1785; rev 2; 3/11 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. *see selector guide for address options. + denotes a lead(pb)-free/rohs-compliant package. pin configuration ordering information part max5360 leuk max5360meuk max5360neuk 0x64 0x62 0x60 address reference +2.0v +2.0v +2.0v adne admy admm top mark max5360peuk 0x66 +2.0v admo max5361 leuk 0x60 +4.0v admu max5361meuk 0x62 +4.0v adna max5361neuk 0x64 +4.0v adng max5361peuk 0x66 +4.0v admq max5362meuk 0x62 0.9 x v dd adnc max5362neuk 0x64 0.9 x v dd adni max5362peuk 0x66 0.9 x v dd adms max5362 leuk 0x60 0.9 x v dd admw selector guide part temp range pin-package max5360_ euk_ +t* -40 c to +85 c5 s ot23- 5 max5361_ euk_ +t* -40 c to +85 c5 s ot23- 5 max5362_ euk_ +t* -40 c to +85 c5 s ot23- 5
max5360/max5361/max5362 low-cost, low-power 6-bit dacs with 2-wire serial interface in sot23 package 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v dd = 2.7v to 3.6v (max5360); v dd = 4.5v to 5.5v (max5361); v dd = 2.7v to 5.5v (max5362); r l =10k , c l = 50pf, t a = t min to t max , unless otherwise noted. typical values are t a = +25?.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v dd to gnd ..............................................................-0.3v to +6v out to gnd ...............................................-0.3v to (v dd + 0.3v) scl, sda to gnd.....................................................-0.3v to +6v maximum current into any pin............................................50ma continuous power dissipation (t a = +70?) 5-pin sot23 (derate 7.1mw/? above +70?)...........571mw operating temperature range max536__euk-t ............................................-40? to +85? storage temperature range .............................-65? to +150? maximum junction temperature .....................................+150? lead temperature (soldering, 10s) .................................+300? soldering temperature (reflow) .......................................+260? code = 0, all digital inputs from 0 to v dd to 1/2lsb, 50k and 50pf load (note 6) positive and negative (note 1) v out = 0 to v dd , power-down mode code = 0, 0 to -100? max5360 code = 63, max5360/max5361 (note 4) code = 63 guaranteed monotonic (note 2) guaranteed monotonic (note 2) max5362 (notes 2, 3) code = 63 conditions nvs 2 digital feedthrough ? 20 output settling time v/? 0.4 voltage output slew rate k 10 output resistance lsb 0.5 output load regulation 1.8 2 2.2 ppm/? ?0 full-scale error temperature coefficient lsb ? inl integral linearity error bits 6 resolution ?0 db 60 full-scale error supply rejection % of ideal fs 5 full-scale error 10 lsb ? dnl differential linearity error mv ? ?5 v os offset error db 60 offset error supply rejection 3 units min typ max symbol parameter from software shutdown code 31 to 32 ? 50 wake-up time nvs 40 digital-analog glitch impulse (note 2) ppm/? 1 offset error temperature coefficient max5360/max5361 max5362 max5360/max5361 max5362 max5360/max5361 max5362 code = 63, 0 to 100? 0.5 max5361 3.6 4 4.4 max5362 v 0.85 0.9 0.95 v dd v dd v dd ref internal reference (note 5) static accuracy dac output dynamic performance
max5360/max5361/max5362 electrical characteristics (continued) (v dd = 2.7v to 3.6v (max5360); v dd = 4.5v to 5.5v (max5361); v dd = 2.7v to 5.5v (max5362); r l =10k , c l = 50pf, t a = t min to t max , unless otherwise noted. typical values are t a = +25?.) max5361 max5360 v ih min to v il max, bus capacitance 10pf to 400pf i sink = 6ma (note 7) i sink = 3ma max5362 no load, all digital inputs at 0 or v dd , code = 63 shutdown mode conditions ns 250 t of output fall time v 0 0.6 v ol output low voltage 0 0.4 ns 050 t sp pulse width of spike suppressed ? ?0 i i input leakage current 4.5 5.5 2.7 3.6 pf 10 c in input capacitance v 0.05 v dd v hys input hysteresis v 0.7 v dd v ih input high voltage v 0.3 v dd v il input low voltage v 2.7 5.5 v dd supply voltage 150 230 ? 1 i dd supply current units min typ max symbol parameter low-cost, low-power 6-bit dacs with 2-wire serial interface in sot23 package _______________________________________________________________________________________ 3 i sink = 3ma i sink = 6ma 250 power requirements digital inputs (scl, sda) digital output (sda) (open drain) conditions ? 0.6 t high high period of the scl clock ? 1.3 t low low period of the scl clock khz 0 400 f scl scl clock frequency ? 0.6 t hd, sta hold time (repeated) start condition ? 1.3 t buf bus-free time between a stop and a start condition units min typ max symbol parameter timing characteristics (v dd = 2.7v to 3.6v (max5360); v dd = 4.5v to 5.5v (max5361); v dd = 2.7v to 5.5v (max5362); r l =10k , c l = 50pf, t a = t max to t min , figure 3, unless otherwise noted. typical values are t a = +25?.)
max5360/max5361/max5362 low-cost, low-power 6-bit dacs with 2-wire serial interface in sot23 package 4 _______________________________________________________________________________________ timing characteristics (continued) (v dd = 2.7v to 3.6v (max5360); v dd = 4.5v to 5.5v (max5361); v dd = 2.7v to 5.5v (max5362); r l =10k , c l = 50pf, t a = t max to t min , figure 3, unless otherwise noted. typical values are t a = +25?.) data hold time t hd, dat 0 0.9 ? data setup time t su, dat 100 ns rise time of both sda and scl signals t r 300 ns fall time of both sda and scl signals t f conditions 300 ns setup time for stop condition t su, sto 0.6 ? capacitive load for each bus line c b 400 pf ? 0.6 t su, sta setup time for a repeated start condition units min typ max symbol parameter note 1: guaranteed from code 1 to code 63. note 2: the offset value extrapolated from the range over which the inl is guaranteed. note 3: max5362, tested at v dd = 5v ?0%. note 4: max5360, tested at v dd = 3v ?0%; max5361, tested at v dd = 5v ?0%. note 5: actual output voltage at full scale is 63/64 v ref . note 6: output settling time is measured by taking the code from code 1 to code 63, and from code 63 to code 1. note 7: guaranteed by design. -0.045 -0.020 -0.030 -0.025 -0.035 -0.040 -0.015 -0.010 -0.005 0 0.005 0.010 0.015 0.020 0.025 0.030 0 255075 integral nonlinearity vs. code max5360/1/2-01 code inl (lsb) 0 -0.025 -0.050 2.5 4.0 3.0 3.5 4.5 5.0 5.5 integral nonlinearity vs. supply voltage max5360/1/2-02 supply voltage (v) inl (lsb) 0 -0.025 -0.050 -40 20 -20 0 40 60 80 100 integral nonlinearity vs. temperature max5360/1/2-03 temperature ( c) inl (lsb) typical operating characteristics (v dd = 3v (max5360), v dd = 5v (max5361/max5362), t a = +25?, unless otherwise noted.)
max5360/max5361/max5362 low-cost, low-power 6-bit dacs with 2-wire serial interface in sot23 package _______________________________________________________________________________________ 5 -0.020 -0.010 -0.015 -0.005 0 0.005 0.010 0 255075 differential nonlinearity vs. code max5360/1/2-04 code dnl (lsb) 0 -0.015 -0.020 -0.010 -0.005 -0.025 2.5 4.0 3.0 3.5 4.5 5.0 5.5 differential nonlinearity vs. supply voltage max5360/1/2-05 supply voltage (v) dnl (lsb) 0 -0.010 -0.015 -0.020 -0.005 -0.025 -40 20 -20 0 40 60 80 100 differential nonlinearity vs. temperature max5360/1/2-06 temperature ( c ) dnl (lsb) -0.20 -0.10 -0.15 -0.05 0 0.05 0.10 0.15 0 255075 total unadjusted error vs. code max5360/1/2-07 code tue (lsb) 0 -0.25 -0.50 2.5 4.0 3.0 3.5 4.5 5.0 5.5 offset error vs. supply voltage max5360/1/2-08 supply voltage (v) v os (mv) 0 -0.25 -0.50 -40 20 -20 0 40 60 80 100 offset error vs. temperature max5360/1/2-09 temperature ( c) v os typical operating characteristics (continued) (v dd = 3v (max5360), v dd = 5v (max5361/max5362), t a = +25?, unless otherwise noted.) 0.75 0.25 0 -0.25 -0.50 0.50 -0.75 2.5 4.0 3.0 3.5 4.5 5.0 5.5 full-scale error vs. temperature max5360/1/2-10 supply voltage (v) full-scale error (lsb) 1.2 0.4 0 -0.4 -0.8 0.8 -1.2 sc o ( ) max5361 max5360 max5362 no load 0.75 0.25 0 -0.25 -0.50 0.50 -0.75 1.2 0.4 0 -0.4 -0.8 0.8 -1.2 -40 20 -20 0 40 60 80 100 full-scale error vs. temperature max5360/1/2-11 temperature ( c) full-scale error (lsb) full-scale error (%) max5362 max5360 max5361 200 140 120 100 60 80 20 40 160 180 0 2.5 4.0 3.0 3.5 4.5 5.0 5.5 supply current vs. supply voltage max5360/1/2-12 supply voltage (v) supply current ( a) max5360 max5361 max5362
max5360/max5361/max5362 low-cost, low-power 6-bit dacs with 2-wire serial interface in sot23 package 6 _______________________________________________________________________________________ 160 150 145 140 135 155 130 -40 20 -20 0 40 60 80 100 supply current vs. temperature max5360/1/2-13 temperature ( c) supply current ( a) max5361 max5362 max5360 160 150 145 140 135 155 130 024 816 3240485664 supply current vs. code max5360/1/2-14 code supply current ( a) max5361 v dd = 5v max5362 v dd = 5v max5360 v dd = 3v max5360 v dd = 5v 1.0 0.4 0.2 0.6 08 0 2.5 4.0 3.0 3.5 4.5 5.0 5.5 shutdown supply current vs. supply voltage max5360/1/2-15 supply voltage (v) supply current ( a) 1.0 0.6 0.4 0.2 0.8 0 -40 20 -20 0 40 60 80 100 shutdown supply current vs. temperature max5360/1/2-16 temperature ( c) supply current ( a) v dd = 5v v dd = 3v 2.0 1.5 2.5 3.0 4.0 3.5 4.5 0 0.1 0.2 02 14 36 589 710 output load regulation max5360/1/2-17 load current (ma) a: max5361/max5362, v dd = 4.5v, full-scale or sourci n b: max5360, full-scale, v dd = 2.7v sinking, v dd = 5v s o c: max5360, full-scale, v dd = 2.7v, sourcing d: zero code, v dd = 2.7v, sinking e: zero code, v dd = 5.5v sinking v out full scale (v) v out zero code (v) a b c d e 4 s/div output voltage on power-up max5360/1/2-18 out 50mv/div v dd 2v/div typical operating characteristics (continued) (v dd = 3v (max5360), v dd = 5v (max5361/max5362), t a = +25?, unless otherwise noted.)
max5360/max5361/max5362 low-cost, low-power 6-bit dacs with 2-wire serial interface in sot23 package _______________________________________________________________________________________ 7 pin description name function 1 out dac voltage output 2 gnd ground pin 3 v dd power-supply input 4 sda serial data input 5 scl serial clock input 10 s/div max5360 output voltage exiting shutdown max5360/1/2-19 out 500mv/div sda 3v/div 1 s/div max5360 output voltage entering shutdown max5360/1/2-20 out 500mv/div sda 3v/div 1 s/div max5360 output settling from 1/4 fs to 3/4 fs max5360/1/2-21 out 0.5v/div sda 3v/div 1 s/div max5360 output settling from 3/4 fs to 1/4 fs max5360/1/2-22 out 0.5v/div sda 3v/div 2 s/div max5360 output settling 1/4lsb step-up max5360/1/2-23 out 20mv/div ac-coupled sda 3v/div 0 x 7f to 0 x 80 01111111 to 10000000 max5360 output settling 1/4lsb step-down max5360/1/2-24 out 20mv/div ac-coupled sda 3v/div 2 s/div 0 x 80 to 0 x 7f 10000000 to 01111111 typical operating characteristics (continued) (v dd = 3v (max5360), v dd = 5v (max5361/max5362), t a = +25?, unless otherwise noted.)
max5360/max5361/max5362 low-cost, low-power 6-bit dacs with 2-wire serial interface in sot23 package 8 _______________________________________________________________________________________ detailed description the max5360/max5361/max5362 voltage-output, 6-bit dacs offer full 6-bit performance with less than 1lsb integral nonlinearity (inl) error and less than 1lsb dif- ferential nonlinearity (dnl) error ensuring monotonic performance. the devices use a simple two-wire, fast- mode i 2 c-compatible serial interface that operates up to 400khz. the max5360/max5361/max5362 include an internal reference, an output buffer, and low-current shutdown mode, making them ideal for low-power, highly integrated applications. figure 1 shows the devices?functional diagram. analog section the max5360/max5361/max5362 employ a current- steering dac topology as shown in figure 2. at the core of the dac is a reference voltage-to-current con- verter (v/i) that generates a reference current. this cur- rent is mirrored to 255 equally weighted current sources. dac switches control the outputs of these cur- rent mirrors, so only the desired fraction of the total cur- rent-mirror currents is steered to the dac output. the current is then converted to a voltage across a resistor, and this voltage is buffered by the output buffer amplifier. output voltage table 1 shows the relationship between the dac code and the analog output voltage. the 6-bit dac code is binary unipolar with 1lsb = (v ref / 64). the max5360/ max5361 have a full-scale output voltage of (+2v - 1lsb) and (+4v - 1lsb), respectively, set by the inter- nal references. the max5362 has a full-scale output voltage of (0.9 v dd - 1lsb). each device accepts 8-bit dac codes, but the accuracy is guaranteed only for 6 bits. output buffer the dac voltage output is an internally buffered unity- gain follower that typically slews at ?.4v/?. the out- put can swing from 0 to full scale. with a 1/4 fs to 3/4 fs output transition, the amplifier outputs typically settle to 1/2lsb in less than 5? when loaded with 10k in parallel with 50pf. the buffer amplifiers are stable with any combination of resistive loads >10k and capaci- tive loads <50pf. v ref out sw1 sw2 sw255 figure 2. current-steering topology v dd out 10k gnd sda scl 255 6 + 2 current- steering dac data latch serial input register control logic max5360 max5361 max5362 ref figure 1. functional diagram table 1. unipolar code current 000001 (00) 0.9 v dd / 64 62mv 31mv 000000 (00) 0 0 0 100000 (00) 0.9 v dd / 2 2v 1v 111111 (00) 0.9 v dd (63/64) 4v (63/64) 2v (63/64) max5362 max5361 max5360 dac code 6 bits + 2 subbits output voltage
max5360/max5361/max5362 low-cost, low-power 6-bit dacs with 2-wire serial interface in sot23 package _______________________________________________________________________________________ 9 power-on reset the max5360/max5361/max5362 have a power-on reset circuit to set the dac? output to 0 when v dd is first applied or when v dd dips below 1.7v. this ensures that unwanted dac output voltages will not occur immediately following a system startup, such as after a loss of power. the output glitch on startup is typically <50mv. shutdown mode the max5360/max5361/max5362 include a software- controlled shutdown mode that reduces the supply cur- rent to <1?. all internal circuitry is disabled and an internal 10k resistor is placed from out to gnd to ensure 0v at out while in shutdown. the device enters shutdown in less than 5? and exits shutdown in less than 50?. digital section serial interface the max5360/max5361/max5362 use a simple two- wire serial interface requiring only two i/o lines (two- wire bus) of a standard microprocessor (?) port. figure 3 shows the timing diagram for signals on the 2- wire bus. the two bus lines (sda and scl) must be high when the bus is not in use. the max5360/max5361/ max5362 are receive-only devices (slaves) and must be controlled by a bus master device. figure 4 shows a typical application where multiple devices can be con- nected to the bus provided they have different address settings. external pullup resistors are not necessary on these lines (when driven by push-pull drivers), though the max5360/max5361/max5362 can be used in applications where pullup resistors are required (such as in i 2 c systems) to maintain compatibility with exist- ing circuitry. the serial interface operates at scl rates up to 400khz. the sda state is allowed to change only while scl is low, with the exception of start and stop conditions as shown in figure 5. each transmis- sion consists of a start condition sent by the bus master device, followed by the max5360/max5361/ max5362? preset slave address, a power-mode bit, the dac data (6 bits + 2 subbits), and finally, a stop scl sda t low t high t f t r t hd , sta t hd , dat t hd , sta t su , dat t su , sta t buf t su , sto start condition stop condition repeated start condition start condition figure 3. two-wire serial interface timing diagram c sda scl r s * v dd offset adjustment threshold adjustment gain adjustment r s * is optional. scl sda v dd out max5360m 2v reference scl sda v dd out max5361n 4v reference scl sda v dd out max5362p v dd reference figure 4. typical application circuit
max5360/max5361/max5362 condition (figure 6). the bus is then free for another transmission. sda? state is sampled, and therefore must remain sta- ble while scl is high. data is transmitted in 8-bit bytes. nine clock cycles are required to transfer each byte to the max5360/max5361/max5362. release sda during the 9th clock cycle as the selected device acknowl- edges the receipt of the byte, by pulling sda low dur- ing this time. a series resistor on the sda line may be needed if the master? output is forced high while the selected device acknowledges (figure 4). slave address the max5360/max5361/max5362 are available with one of four preset slave addresses. each address option is identified by the suffix l, m, n, or p added to the part number. the address is defined as the 7 most significant bits (msbs) sent by the master after a start condition. the address options are 0x60, 0x62, 0x64, and 0x66 (left justified with lsb set to 0). the 8th bit, typically used to define a write or read protocol, sets the device? power mode (shdn); the device is powered down when shdn is set to 1. during a device search routine, the max5360/max5361/max5362 acknowledge both options (shdn = 0 or shdn = 1) but does not change its power state if a stop condition (or restart) is issued immediately. the second byte (dac data) must be sent/received for the device to update both power mode and dac output. dac data the 6-bit dac data is decoded as straight binary msb first with 1lsb = (v ref / 64) and converted into the cor- responding analog voltage as shown in table 1. two subbits complete the data byte; these 2 bits should be set to zero since they are not tested to guaranteed- monotonic performance. after receiving the data byte, the max5360/max5361/ max5362 acknowledge its receipt and expect a stop condition, at which point the dac output is updated. the devices update the output and the power mode only if the second byte is clocked in (shdn = 0) or out (shdn = 1) of the device. when shdn = 1, the master will read all ones when clocking out a data byte. the max5360/max5361/max5362 do not drive sda except for the acknowledge bit. low-cost, low-power 6-bit dacs with 2-wire serial interface in sot23 package 10 ______________________________________________________________________________________ scl sda start condition stop condition 1 3 2 4 6 5 7 9 8 10 12 11 13 15 14 16 18 17 ack lsb msb lsb msb 0 1 1 0 x 0 x ack shdn d6 d3 d4 d2 d0 d1 s1 s0 slave address byte dac code figure 6. complete serial transmission scl sda start condition stop condition figure 5. start and stop conditions
i 2 c compatibility the max5360/max5361/max5362 are compatible with existing i 2 c systems. scl and sda are high-imped- ance inputs; sda has an open drain that pulls the data line low during the 9th clock pulse. figure 7 shows a typical i 2 c application. the communication protocol supports the standard i 2 c 8-bit communications. the general call address is ignored, and cbus formats are not supported. the max5360/max5361/max5362 address is compatible with the 7-bit i 2 c addressing protocol only. no 10-bit formats are supported. restart protocol is supported, but an immediate stop condition is necessary to update the dac. applications information digital inputs and interface logic the serial 2-wire interface has logic levels defined as v ol = 0.3 x v dd and v oh = 0.7 x v dd . all of the inputs include schmitt-trigger buffers to accept slow-transition interfaces. this means that optocouplers can interface directly to the max5360/max5361/max5362 without additional external logic. the digital inputs are compati- ble with cmos logic levels and must not be driven with voltages higher than v dd . power-supply bypassing and layout careful pc board layout is important for best system performance. to reduce crosstalk and noise injection, keep analog and digital signals separate. ensure that the ground return from gnd to the supply ground is short and low impedance; a ground plane is recom- mended. bypass v dd with a 0.1? to ground as close as possible to the device. if the supply is excessively noisy, connect a 10 resistor in series with the supply and v dd , and add additional capacitance max5360/max5361/max5362 low-cost, low-power 6-bit dacs with 2-wire serial interface in sot23 package ______________________________________________________________________________________ 11 c sda scl v dd offset adjustment threshold adjustment gain adjustment scl sda v dd out max5360l 2v reference scl sda v dd out max5361m 4v reference scl sda v dd out max5362p v dd reference figure 7. i 2 c typical application process: bicmos chip information
max5360/max5361/max5362 low-cost, low-power 6-bit dacs with 2-wire serial interface in sot23 package 12 ______________________________________________________________________________________ package information for the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages . note that a ?? ?? or ??in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing per - tains to the package regardless of rohs status. package type package code outline no. land pattern no. 5 sot23 u5+1 21-0057 90-0174
maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 13 2011 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. max5360/max5361/max5362 low-cost, low-power 6-bit dacs with 2-wire serial interface in sot23 package revision history revision number revision date description pages changed 2 3/11 corrected offset error specification in electrical characteristics table 2

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